1. Field of the Invention
The invention relates to a serial data transfer device which conducts the transmission and reception of serial data, and particularly to a serial data transfer device having a FIFO memory which can store plural transmit data and receive data.
2. Description of Related Art
In order to continuously transfer serial data, a prior art serial data transfer device comprises a memory which can store plural transfer data. As such a memory, a FIFO memory having the first-in first-out function or pushup storage function is used.
FIG. 1 shows a prior art example which is a serial data transfer mechanism used in a data processor (type MC68332) produced by Motorola Inc.
In FIG. 1, the reference numeral 80 designates a data serializer which converts a serial data inputted from the outside into a parallel data and outputs the parallel data to a RAM 79, and which receives a parallel data written from the outside into the RAM 79, converts the parallel data to a serial data, and outputs the serial data to the outside. The RAM 79 stores parallel data from the data serializer 80, and outputs the parallel data to the outside. Furthermore, the RAM 79 stores parallel data inputted from the outside, and outputs the parallel data to the data serializer 80.
The reference numeral 71 designates a cue pointer indicating the number of entries in which data are stored in the RAM 79. The cue pointer 71 outputs the number of the entries to an address register 78 and a comparator 72. The address register 78 outputs the number of entries to the RAM 79. The reference numeral 73 designates an end cue pointer indicating the number of the entries in the RAM 79 at the time when the transfer in the RAM 79 is completed. The comparator 72 compares the output value of the cue pointer 71 with the set value of the end cue pointer 78. When the two values coincide with each other, the comparator 72 outputs an interrupt signal.
The reference numeral 81 designates a clock generator which generates a clock signal SCK for data sampling or sending. A status register 74 for setting a transmission/receive completion flag, an error flag, etc., a control register 75 for controlling the transmission/reception permission, and a delay counter 76 for delaying the generation of the clock signal SCK in the clock generator 81 are connected to a control PLA 77.
Hereinafter, the interruption in the receiving operation in the prior art serial data transfer device having such a configuration will be described.
A serial data inputted from the outside is converted into a parallel data by the data serializer 80, and then stored in the RAM 79. The final absolute address at which the transfer is to be completed is previously written into the end cue pointer 73. Each time the transfer is completed, the comparator 72 compares the value of the cue pointer 71 with that of the end cue pointer 73. When the two values coincide with each other, a receive completion flag is set, and an interrupt signal appears.
As described above, according to the prior art example, in a transfer process of receiving (or transmitting) plural serial data, the interrupt signal doesn't appear until the receive (or transmission) is completed. In other words, there is a problem in that, in a transfer process of receiving (or transmitting) plural serial data, particularly, in the course of a continuous transfer, the interrupt signal can't be appeared at the receive (or transmission) completion of an arbitrary number of data.